Improving Development Scheduling and Cost Flow in SEER-H
SEER for Hardware is a leading hardware cost estimating and planning system. Until recently, SEER HW had basic visibility into the scheduling of estimates, limited to annual expenditure. An upcoming version of SEER HW will include a set of new features to help program managers better schedule tasks and manage their expenditures. This effort, sponsored in part by NASA IPAO, will be part of the 7.1 release of the SEER HW product.
The advanced schedule features cover areas such as allocation into program phases (e.g. preliminary design, detailed design, system validation) with the ability to independently schedule them. Scheduling of the development effort can be constrained by such things as a slow start, overstaffing, and understaffing, shortened or extended schedules. Depending on the scenario, cost penalties can be incurred for various types of constraints.
This presentation will review the concepts, theory and methods used to implement this comprehensive set of features. Examples of how these features can be used will be provided along with how they can benefit a cost analyst or project manager.
Ainsley Chong is a Systems Engineer/Cost Analyst for Galorath Incorporated. He works primarily on the SEER for Hardware estimation suite, and was the lead analyst for the development of Integrated Circuits Pro [SEER-IC], an optional addin for SEER-HW. He is currently working with Evin Stump on the development of the XIPRR model, estimating project risk parametrically.
Mr. Chong holds the BS in Computer Engineering from the University of California at Los Angeles.