Adding Process Tailoring to Product Size for Better Cost Estimation
Generally, when one is looking to create a parametric model to predict costs of an activity, then one looks to size relationships associated with that activity. For example, if one were to develop a parametric model for estimating the development of a Field Programmable Gate Array (FPGA), then, because most of the work to complete an FPGA revolves around software code development, building a parametric model around new code, modified code and reused code (with other size relationships) would probably be a good place to start.
However, as many aerospace organizations are incorporating the Capability Maturity Model Integration (CMMI) approach to process improvement, there is now substantially more development activity information available to parametric model development than just size (size being the number of lines of FPGA code). Further, there are normally pre-tailored process lists for any product type associated with an end application (such as manned flight FPGAs or space FPGAs).
This paper looks at the ability to incorporate repeatable processes into simple parametric models in order to improve the predictive capability. This paper will not be a rigorous mathematical approach into Bayesian statistics, but will be focus on the simple concepts of associating the effort to improve process repeatability that many aerospace organizations have made to become CMMI level 5 compliant with the ability to improve cost estimation practices.
After graduating from the University of California at Davis in 1983, Mr. Bloom has worked for the Naval Weapons Center, Lockheed Martin, Lawrence Livermore National Labs and since 2008, for Raytheon Space and Airborne Systems (SAS) where he is a Sr. Engineering Manager.
Mr. Bloom is currently the Cost Estimation Subject Matter Expert (SME) for the Electronics Center of SAS. He has developed parametric models for all Electronics Center products and helped transform the culture of the organization in the use of parametric bidding methodologies.
In addition to Mr. Bloom’s focus for the Electronics Center in developing parametric cost models for the design and development cycle activity of electronics sub-products, he is also leading the effort to reduce the cost of FPGA and ASIC development by modernizing the Digital Verification methods and establishing reproducible re-use methods.
Mr. Bloom has 2 patents and a software copyright along with a number of publications ranging from electromagnetic boundary value problems to cost estimation. In 2006, he won the International R&D 100 Award for innovating a cost effective Gigapixel Camera for persistent surveillance applications.